1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit with a logic circuit including a data holding circuit, such as a latch circuit or a flip-flop, which has reduced the occurrence of soft errors caused by, for example, a rays or neutron radiation.
2. Description of the Related Art
Soft errors in a semiconductor device caused by a rays or neutron radiation have been acknowledged as a problem in the semiconductor devices installed in the equipment used mainly in the space field and in the aircraft field. In a memory cell, there has been provided an error-correction code to detect and correct a soft error, even if a soft error has occurred.
In recent years, with the higher integration and further miniaturization of semiconductor devices, the parasitic capacitance of a cell becomes small to the extent that the occurrence of a soft error cannot be ignored even in a semiconductor device used on earth. Therefore, even in a logic circuit, measures should be taken against soft errors. In a circuit for holding data, such as a latch circuit or a flip-flop, if the held data is inverted and the inverted data is held, the inverted data propagates and has a greater effect on the operation of the chip. Therefore, measures against soft errors in the data holding circuit are required.
As for measures against soft errors in a data holding circuit, circuits provided with the measures have been disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2003-273709 (hereinafter, referred to as reference 1). The configuration of each of the circuits is such that the held data is corrected on the basis of the fact that only an error from “0” to “1” occurs in a p-channel MOS transistor and that only an error from “1” to “0” occurs in an n-channel MOS transistor.
The circuit configurations shown in FIGS. 6 and 25 in reference 1 are dynamic data holding circuits. It is expected that the data is not retained by parasitic capacitance and that the data is not changed by a leakage current in the transistor. However, in dynamic data holding circuits, the stability changes according to the value of the parasitic capacitance or to the magnitude of a leakage current in the transistor. If the parasitic capacitance is small, or if a leakage current in the transistor is large, the data can be changed in the very worst case.
In contrast, in a static data holding circuit, since either “0” or “1” is always held in a loop circuit composed of a feedback circuit, the holding circuit is very stable against parasitic capacitance and a leakage current in the transistor. However, the circuits shown in FIGS. 8 and 12 in reference 1, which are formed of static data holding circuits, have the problem of having a complex configuration and a large circuit size because a large number of transistors have been used.